1. Field of Invention
Various embodiments of the present invention relate to a non-volatile memory device and a method for erasing the same, and more specifically, to a non-volatile memory device including a vertical channel and a method for erasing the same.
2. Discussion of Related Art
Non-volatile memory devices are used as data storage devices in various electronic devices, such as computers, laptops, and mobile phones. These electronic devices are gradually becoming light-weight. As demand for mass-storage devices increases, NAND flash memory devices are primarily used in the devices.
Conventional NAND flash memory devices include a plurality of memory cells arranged in a direction parallel to a semiconductor substrate, this is known as a two-dimensional semiconductor memory device. However, since a semiconductor memory device with a two-dimensional structure has a limit for increasing integration, semiconductor memory device is being developed that includes a plurality of memory cells vertically stacked on the semiconductor substrate. These are known as a 3D semiconductor memory device or a semiconductor memory device that includes a vertical channel layer, hereinafter, referred to as a three-dimensional semiconductor memory device.
In terms of enhanced integration, the three-dimensional semiconductor memory device is superior to the two-dimensional semiconductor memory device.
Particularly, the three-dimensional semiconductor memory device includes a plurality of memory cells vertically stacked on the semiconductor substrate, and a channel that includes a vertical channel layer extending in a vertical direction with respect to the semiconductor substrate. To form the vertical channel layer, a hole is formed. However, due to the nature of an etching process for forming the hole, a width of the hole is narrower toward a lower portion than an upper portion. During an erase operation using a gate induced drain leakage (“GIDL”) current, such a structure may cause an electrical difference between memory cells formed at the upper portion and the memory cells formed at the lower portion.